DPRAM
//-------------------------------------DPRAM--------------------------------------------------------------- module dpram(clk,rst,read_en,read_addr,wr_addr,wr_data,wr_en,read_data); output reg [15:0] read_data; input clk,rst,read_en,wr_en; input [4:0] wr_addr,read_addr; input [15:0]wr_data; reg [15:0] memory[31:0]; integer i; always @(posedge clk,negedge rst) begin if(!rst) begin for(i=0;i<32;i=i+1) begin memory[i]<=0; end end else begin if(read_en) read_data<=memory[read_addr]; if(wr_en) memory[wr_addr]<=wr_data; end end endmodule //------------------------------------testbench-------------------------------------------------------------- module ram_tb(); integer i; wire [15:0]read_data; reg clk,rst,read_en,wr_en; reg [15:0] wr_data; reg [4:0] wr_addr,read_addr; dpram DUT(clk,rst,read_en,read_addr,wr_addr,wr_data,wr_en,read_data); task initialize; beg